This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-347711, filed Nov. 15, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an active matrix liquid crystal display apparatus in which a cross talk can be reduced.
2. Description of the Related Art
FIG. 3 is a partially see through, plan view of a part of an exemplary conventional active matrix liquid crystal display apparatus. The active matrix liquid crystal display apparatus includes a glass substrate 1. A plurality of scanning signal lines 2 and data signal lines 3 are disposed on an upper surface of the glass substrate 1 in a matrix form. A thin-film transistor 4 and pixel electrode 5 are disposed in the vicinity of each of intersections of the lines, and an auxiliary capacity line 6 is disposed in parallel to the scanning signal line 2 under an upper side of the pixel electrode 5.
The pixel electrodes 5 are delta-arranged. That is, three colors i.e. red (R), green (G), and blue (B) pixel electrodes 5 constituting one pixel are disposed in positions corresponding to one of vertexes of an isosceles triangle (Greek character xcex94) respectively. Therefore, the scanning signal line 2 linearly extends in a row direction between the upper and lower pixel electrodes 5 (FIG. 3), and the data signal line 3 is disposed in a meandered manner in a column direction between the left and right pixel electrodes 5 (FIG. 3) and between the upper and lower pixel electrodes 5.
A concrete structure of the active matrix liquid crystal display apparatus will next be described with reference to FIG. 4. FIG. 4 is a sectional view taken along line IVxe2x80x94IV of FIG. 3. The scanning signal lines 2 including gate electrodes 11 are disposed in predetermined positions on the upper surface of the glass substrate 1, each of the auxiliary capacity lines 6 is disposed in another predetermined position, and a gate insulating film 12 of silicon nitride is disposed on the whole upper surface of the substrate. A semiconductor thin film 13 of intrinsic amorphous silicon is disposed in a predetermined position on the upper surface of the gate insulating film 12 on the gate electrode 11. A channel protection film 14 of silicon nitride is disposed in a predetermined position on the upper surface of the semiconductor thin film 13. Ohmic contact layers 15, 16 of n-type amorphous silicon are disposed on opposite sides of the upper surface of the channel protection film 14 and on the upper surface of the semiconductor thin film 13 on the opposite sides of the channel protection film.
The data signal line 3 including a drain electrode 17 is disposed in a predetermined position on the upper surface of one ohmic contact layer 16 and on the upper surface of the gate insulating film 12. In this case, the data signal line 3 has a three-layered structure of an intrinsic amorphous silicon film 3a, n-type amorphous silicon film 3b, and metal film 3c. When the semiconductor thin film 13 is formed, the intrinsic amorphous silicon film 3a is simultaneously formed by the same film as the semiconductor thin film 13. When the ohmic contact layers 15, 16 are formed, the n-type amorphous silicon film 3b is simultaneously formed by the same film as the ohmic contact layers 15, 16. When the drain electrode 17 is formed of metal such as chromium, the metal film 3c is simultaneously formed by the same film as the drain electrode 17.
A source electrode 18 of chromium, and the like is disposed on the upper surface of the other ohmic contact layer 15. Here, the gate electrode 11, gate insulating film 12, semiconductor thin film 13, channel protection film 14, ohmic contact layers 15, 16, drain electrode 17, and source electrode 18 constitute the thin film transistor 4. A flatted film (interlayer insulating film) 19 of resin is disposed on the whole upper surface of the gate insulating film 12 including the thin film transistor 4. The pixel electrode 5 of ITO is disposed in a predetermined position on the upper surface of the flatted film 19. The pixel electrode 5 is connected to the source electrode 18 via a contact hole 20 formed in the flatted film 19.
In the aforementioned conventional active matrix liquid crystal display apparatus, the flatted film 19 of the resin is formed by a spin coat process, and the film is formed to be relatively thick in about several micrometers. Therefore, even when the pixel electrode 5 is superposed upon the data signal line 3, no short-circuit occurs between the pixel electrode 5 and the data signal line 3. For the data signal line 3, a width of a portion extending in the column direction is set to be slightly larger than a width of a portion extending in the row direction. Opposite ends of a width direction of the data signal line 3 having a large width and extending in the column direction are superposed upon adjacent side portions of the pixel electrodes 5 disposed adjacent to the data signal line in a left-to-right direction. Moreover, a function of a shield film is imparted to the data signal line 3 extending in the column direction, and this increases an opening ratio. In one example, an interval G of two pixel electrodes 5 adjacent to each other in the left-to-right direction is set to a minimum interval of 4 xcexcm to such an extent that any short-circuit does not occur between the pixel electrodes. Moreover, in consideration of an alignment precision, and the like, an overlap width L of the pixel electrode 5 and data signal line 3 is designed to be 2 xcexcm so that the electrode and line overlap with each other in any case. Then, a minimum width W of the data signal line 3 is 8 xcexcm.
As described above, in the conventional active matrix liquid crystal display apparatus, the opposite ends of the width direction of the data signal line 3 extending in the column direction are superposed upon the adjacent side portions of the pixel electrodes 5 disposed adjacent to each other in the left-to-right direction, and the function of the shield film is imparted to the data signal line 3 extending in the column direction. However, when an area of one pixel electrode 5 is reduced for a highly fine pixel, a vertical cross talk is recognized. That is, when the pixel electrode 5 and data signal line 3 are superposed upon each other, a parasitic capacity Cds increases, and the increase of parasitic capacity Cds is a factor for causing the vertical cross talk. It is known that a ratio xcex2 of the parasitic capacity Cds to a total accumulated capacity Cp of one pixel electrode 5 is xcex2=Cds/Cp=Cds/(Cds+Clc+Cs+Cgs). When the ratio xcex2 is reduced, the vertical cross talk is securely prevented from occurring. Here, Clc is a capacity of a liquid crystal between one pixel electrode 5 and an opposite electrode (not shown), Cs is an accumulated capacity (hereinafter referred to as an auxiliary capacity) between the pixel electrode 5 and the auxiliary capacity line 6, and Cgs is a parasitic capacity between the pixel electrode 5 and the scanning signal line 2. However, since the active matrix liquid crystal display apparatus tends to be gradually highly refined, and the area of the pixel electrode is accordingly reduced, Clc is reduced, and the vertical cross talk increasingly becomes conspicuous.
An object of the present invention is to reduce a parasitic capacity Cds between a pixel electrode and a data signal line so that a cross talk becomes inconspicuous.
According to the present invention, there is provided an active matrix liquid crystal display apparatus comprising: a substrate; a plurality of pixel electrodes formed on the substrate; a plurality of switching elements electrically connected to the pixel electrodes, respectively; a plurality of data signal lines connected to the switching elements; a first insulating layer disposed between the data signal lines and the pixel electrodes; an auxiliary capacity line partially overlapping with each pixel electrode; and a second insulating layer disposed between the data signal lines and the auxiliary capacity lines, each auxiliary capacity line having a portion overlapping with the data signal line, the portion having a width larger than a width of the data signal line disposed right above the auxiliary capacity line, and overlapping with a peripheral edge of the pixel electrode.